Parasitic Substrate Coupling in High Voltage Integrated Circuits
- Minority and Majority Carriers Propagation in Semiconductor Substrate
- Indbinding:
- Hardback
- Sideantal:
- 183
- Udgivet:
- 22. marts 2018
- Udgave:
- 12018
- Vægt:
- 477 g.
- 8-11 hverdage.
- 10. december 2024
På lager
Normalpris
Abonnementspris
- Rabat på køb af fysiske bøger
- 1 valgfrit digitalt ugeblad
- 20 timers lytning og læsning
- Adgang til 70.000+ titler
- Ingen binding
Abonnementet koster 75 kr./md.
Ingen binding og kan opsiges når som helst.
- 1 valgfrit digitalt ugeblad
- 20 timers lytning og læsning
- Adgang til 70.000+ titler
- Ingen binding
Abonnementet koster 75 kr./md.
Ingen binding og kan opsiges når som helst.
Beskrivelse af Parasitic Substrate Coupling in High Voltage Integrated Circuits
This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.
The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.
The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.
Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;
Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;
Offers design guidelines to reduce couplings by adding specific protections.
The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.
The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.
Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;
Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;
Offers design guidelines to reduce couplings by adding specific protections.
Brugerbedømmelser af Parasitic Substrate Coupling in High Voltage Integrated Circuits
Giv din bedømmelse
For at bedømme denne bog, skal du være logget ind.Andre købte også..
Find lignende bøger
Bogen Parasitic Substrate Coupling in High Voltage Integrated Circuits findes i følgende kategorier:
© 2024 Pling BØGER Registered company number: DK43351621