Loop Tiling for Parallelism
- Indbinding:
- Hardback
- Sideantal:
- 280
- Udgivet:
- 31. august 2000
- Størrelse:
- 160x20x241 mm.
- Vægt:
- 588 g.
- 8-11 hverdage.
- 21. november 2024
På lager
Normalpris
Abonnementspris
- Rabat på køb af fysiske bøger
- 1 valgfrit digitalt ugeblad
- 20 timers lytning og læsning
- Adgang til 70.000+ titler
- Ingen binding
Abonnementet koster 75 kr./md.
Ingen binding og kan opsiges når som helst.
- 1 valgfrit digitalt ugeblad
- 20 timers lytning og læsning
- Adgang til 70.000+ titler
- Ingen binding
Abonnementet koster 75 kr./md.
Ingen binding og kan opsiges når som helst.
Beskrivelse af Loop Tiling for Parallelism
Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines.
Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones;
Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability;
Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation;
A complete suite of techniques for generating SPMD code for a tiled loop nest;
Up-to-date results on tile size and shape selection for reducing communication and improving parallelism;
End-of-chapter references for further reading.
Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.
Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones;
Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability;
Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation;
A complete suite of techniques for generating SPMD code for a tiled loop nest;
Up-to-date results on tile size and shape selection for reducing communication and improving parallelism;
End-of-chapter references for further reading.
Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.
Brugerbedømmelser af Loop Tiling for Parallelism
Giv din bedømmelse
For at bedømme denne bog, skal du være logget ind.Andre købte også..
Find lignende bøger
Bogen Loop Tiling for Parallelism findes i følgende kategorier:
© 2024 Pling BØGER Registered company number: DK43351621