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Logic Synthesis and Verification Algorithms

Bag om Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

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  • Sprog:
  • Engelsk
  • ISBN:
  • 9781475770360
  • Indbinding:
  • Paperback
  • Sideantal:
  • 564
  • Udgivet:
  • 18. marts 2013
  • Udgave:
  • 11996
  • Størrelse:
  • 178x254x31 mm.
  • Vægt:
  • 1126 g.
  • 8-11 hverdage.
  • 6. december 2024
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Beskrivelse af Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

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