Die-stacking Architecture
- Indbinding:
- Paperback
- Sideantal:
- 128
- Udgivet:
- 10. juni 2015
- Størrelse:
- 191x8x235 mm.
- Vægt:
- 255 g.
- 8-11 hverdage.
- 20. november 2024
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- 1 valgfrit digitalt ugeblad
- 20 timers lytning og læsning
- Adgang til 70.000+ titler
- Ingen binding
Abonnementet koster 75 kr./md.
Ingen binding og kan opsiges når som helst.
Beskrivelse af Die-stacking Architecture
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.
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