Bøger i Synthesis Lectures on Emerging Engineering Technologies serien

This book offers a comprehensive review of innovative measurement and monitoring solutions based on time domain reflectometry (TDR). This technique has numerous applications in several fields, ranging from the characterization of electronic devices to quality control of vegetable oils. However, most of the well-established TDR-based monitoring solutions rely on local or punctual probes; therefore, typically, to monitor large areas/volumes, a high number of probes must be employed, with the consequent maintenance and management requirements. On such bases, in the last few years, the authors have carried out extensive research on the use of diffused wire-like sensing elements to be used as probes for TDR measurements. The basic idea has been to extend the principles of punctual TDR-based monitoring to multi-purpose networks of diffused, sensing elements (SE's), embedded permanently within the systems to be monitored (STBM's). These SEs can be tens of meters long, and can follow any desired path inside the STBM.; in fact, they are inactive inside the STBM. Additionally, these SE's are passive (i.e., they do not require batteries) and their sensing ability is activated, by the TDR signal, when they are connected to the measurement instrument. In addition to this, these SE's are completely maintenance-free. Starting from these considerations, this book addresses the use of low-cost, passive, flexible, wire-like SE's to be used in conjunction with TDR. This book also provides several application test cases, with hints for practical implementation of the described monitoring systems.

Plasma-based techniques are widely and successfully used across the field of materials processing, advanced nanosynthesis, and nanofabrication. The diversity of currently available processing architectures based on or enhanced by the use of plasmas is vast, and one can easily get lost in the opportunities presented by each of these configurations. This mini-book provides a concise outline of the most important concepts and architectures in plasma-assisted processing of materials, helping the reader navigate through the fundamentals of plasma system selection and optimization. Architectures discussed in this book range from the relatively simple, user-friendly types of plasmas produced using direct current, radio-frequency, microwave, and arc systems, to more sophisticated advanced systems based on incorporating and external substrate architectures, and complex control mechanisms of configured magnetic fields and distributed plasma sources.

Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100-300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 ??m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and maximum drain current is an important device attribute to model at lower operating substrate temperatures. This book is the first to illustrate the fact that a single subthreshold slope value which is generally reported in textbook plots and research articles, is erroneous and at lower gate voltage below inversion, subthreshold slope value exhibits a variation tendency on applied gate voltage below threshold, i.e., varying depletion layer and vertical field induced surface band bending variations at the MOSFET channel surface. The author also will critically review the state-of-the art effectiveness of certain device architectures presently prevalent in the semiconductor industry below 45 nm node from the perspectives of device physical analysis at lower substrate temperature operating conditions. The book concludes with an emphasis on modeling simulations, inviting the device professionals to meet the performance bottlenecks emanating from inceptives present at these lower temperatures of operation of today's 10 nm device architectures.

Silicon-on-Insulator (SOI) technology is widely used in high-performance and low-power semiconductor devices. The SOI wafers have two layers of active silicon (Si), and normally the bottom Si layer is a mere physical structure. The idea of making intelligent pixel detectors by using the bottom Si layer as sensors for X-ray, infrared light, high-energy particles, neutrons, etc. emerged from very early days of the SOI technology. However, there have been several difficult issues with fabricating such detectors and they have not become very popular until recently.This book offers a comprehensive overview of the basic concepts and research issues of SOI radiation image detectors. It introduces basic issues to implement the SOI detector and presents how to solve these issues. It also reveals fundamental techniques, improvement of radiation tolerance, applications, and examples of the detectors.Since the SOI detector has both a thick sensing region and CMOS transistors in a monolithic die, many ideas have emerged to utilize this technology. This book is a good introduction for people who want to develop or use SOI detectors.

Exa-scale computing needs to re-examine the existing hardware platform that can support intensive data-oriented computing. Since the main bottleneck is from memory, we aim to develop an energy-efficient in-memory computing platform in this book. First, the models of spin-transfer torque magnetic tunnel junction and racetrack memory are presented. Next, we show that the spintronics could be a candidate for future data-oriented computing for storage, logic, and interconnect. As a result, by utilizing spintronics, in-memory-based computing has been applied for data encryption and machine learning. The implementations of in-memory AES, Simon cipher, as well as interconnect are explained in details. In addition, in-memory-based machine learning and face recognition are also illustrated in this book.

This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.

RRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM). This lecture is a comprehensive tutorial of metal oxide-based RRAM technology from device fabrication to array architecture design. State-of-the-art RRAM device performances, characterization, and modeling techniques are summarized, and the design considerations of the RRAM integration to large-scale array with peripheral circuits are discussed. Chapter 2 introduces the RRAM device fabrication techniques and methods to eliminate the forming process, and will show its scalability down to sub-10 nm regime. Then the device performances such as programming speed, variability control, and multi-level operation are presented, and finally the reliability issues such as cycling endurance and data retention are discussed. Chapter 3 discusses the RRAM physical mechanism, and the materials characterization techniques to observe the conductive filaments and the electrical characterization techniques to study the electronic conduction processes. It also presents the numerical device modeling techniques for simulating the evolution of the conductive filaments as well as the compact device modeling techniques for circuit-level design. Chapter 4 discusses the two common RRAM array architectures for large-scale integration: one-transistor-one-resistor (1T1R) and cross-point architecture with selector. The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array. Chapter 5 is a brief summary and will give an outlook for RRAM's potential novel applications beyond the NVM applications.

Ever since its invention in the 1980s, the compound semiconductor heterojunction-based high electron mobility transistor (HEMT) has been widely used in radio frequency (RF) applications. This book provides readers with broad coverage on techniques and new trends of HEMT, employing leading compound semiconductors, III-N and III-V materials. The content includes an overview of GaN HEMT device-scaling technologies and experimental research breakthroughs in fabricating various GaN MOSHEMT transistors. Readers are offered an inspiring example of monolithic integration of HEMT with LEDs, too. The authors compile the most relevant aspects of III-V HEMT, including the current status of state-of-art HEMTs, their possibility of replacing the Si CMOS transistor channel, and growth opportunities of III-V materials on an Si substrate. With detailed exploration and explanations, the book is a helpful source suitable for anyone learning about and working on compound semiconductor devices.

In order to sustain Moore's Law-based device scaling, principal attention has focused on toward device architectural innovations for improved device performance as per ITRS projections for technology nodes up to 10 nm. Efficient integration of lower substrate temperatures (

In 1965, Intel co-founder Gordon Moore, in ""Cramming more components onto Integrated Circuits"" in Electronics Magazine (April 19, 1965), made the observation that, in the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years. Since its inception in 1965 until recent times, this law has been used in the semiconductor industry to guide investments for long-term planning as well as to set targets for research and development. These investments have helped in a productive utilization of wealth, which created more employment opportunities for semiconductor industry professionals. In this way, the development of Moore's Law has helped sustain the progress of today's knowledge-based economy. While Moore's Law has, on one hand, helped drive investments toward technological and economic growth, thereby benefiting the consumers with more powerful electronic gadgets, Moore's Law has indirectly also helped to fuel other innovationsin the global economy. However, the Law of diminishing returns is now questioning the sustainability of further evolution of Moore's Law and its ability to sustain the progress of today's knowledge based economy. The lack of liquidity in the global economy is truly bringing the entire industry to a standstill and the dark clouds of an economic depression are hovering over the global economy. What factors have been ignored by the global semiconductor industry leading to a demise of Moore's Law? Do the existing business models prevalent in the semiconductor industry pose any problems? Have supply chains made that progress unsustainable? In today's globalized world, have businesses been able to sustain national interests while driving the progress of Moore's Law? Could the semiconductor industry help the entire global economy move toward a radiance of the new crimson dawn, beyond the veil of the darkest night by sustaining the progress of Moore's Law? The entire semiconductor industry isnow clamoring for a fresh approach to overcome existing barriers to the progress of Moore's Law, and this book delivers just that. Moore's Law can easily continue for the foreseeable future if the chip manufacturing industry becomes sustainable by having a balanced economy. The sustainable progress of Moore's Law advocates the ""heresy"" of transforming the current economic orthodoxy of monopoly capitalism into free-market capitalism. The next big thing that everybody is looking forward to after mobile revolution is the ""Internet of Things"" (IoT) revolution. While some analysts forecast that the IoT market would achieve 5.4 billion connections worldwide by 2020, the poor consumer purchasing power in global economy makes this forecast truly questionable. Sustaining Moore's Law presents a blueprint for sustaining the progress of Moore's Law to bring about IoT Revolution in the global economy.

As technologists, we are constantly exploring and pushing the limits of our own disciplines, and we accept the notion that the efficiencies of new technologies are advancing at a very rapid rate. However, we rarely have time to contemplate the broader impact of these technologies as they impact and amplify adjacent technology disciplines.This book therefore focuses on the potential impact of those technologies, but it is not intended as a technical manuscript. In this book, we consider our progress and current position %toward on arbitrary popular concepts of future scenarios rather than the typical measurements of cycles per second or milliwatts. We compare our current human cultural situation to other past historic events as we anticipate the future social impact of rapidly accelerating technologies.We also rely on measurements based on specific events highlighting the breadth of the impact of accelerating semiconductor technologies rather than the specific rate of advance of any particular semiconductor technology.These measurements certainly lack the mathematic precision and repeatability to which technologists are accustomed, but the material that we are dealing with¿the social objectives and future political structures of humanity¿does not permit a high degree of mathematic accuracy.Our conclusion draws from the concept of Singularity. It seems certain that at the rate at which our technologies are advancing, we will exceed the ability of our post¿Industrial Revolution structures to absorb these new challenges, and we cannot accurately anticipate what those future social structures will resemble.