Bøger af Fabio Somenzi

The refereed proceedings of the 15th International Conference on Computer Aided Verification, CAV 2003, held in Boulder, CO, USA in July 2003.The 32 revised full papers and 9 tool papers presented were carefully reviewed and selected from a total of 102 submissions. The papers are organized in topical sections on bounded model checking; symbolic model checking; games, trees, and counters; tools; abstraction; dense time; infinite state systems; applications; theorem proving; automata-based verification; invariants; and explicit model checking.

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

This book summarizes recent research on abstraction techniques for model checking large digital system. Considering the size of today's digital systems and the capacity of state-of-the-art verification algorithms, abstraction is the only viable solution for the successful application of model checking techniques to industrial-scale designs.