Bøger i Analog Circuits and Signal Pro serien

In recent years, we have witnessed a revolutionary change in biomedical signal monitoring. The traditional way of using bulky instruments is being replaced by portable and even wearable acquisition systems with wireless data transmission that will enable many non-clinical applications that rely on biomedical signal monitoring. The main driver applications are early-warning systems, wellness, comfort and sports monitoring, brain-computer interfaces, gaming and entertainment. The common requirements from all these applications are miniature size, unobtrusiveness, high signal quality, and long-term power autonomy. This requires ultra-low-power and miniature SiP/SoC biomedical signal acquisition systems. Biopotential Readout Circuits for Portable Acquisition Systems describes one of the main building blocks of such miniaturized biomedical signal acquisition systems. The focus of this book is on the implementation of low-power and high-performance integrated circuit building blocks that can be used to extract biopotential signals from conventional biopotential electrodes. New instrumentation amplifier architectures are introduced and their design is described in detail. These amplifiers are used to implement complete acquisition demonstrator systems that are a stepping stone towards practical miniaturized and low-power systems.

Advanced Design Techniques for RF Power Amplifiers provides a deep analysis of theoretical aspects, modelling, and design strategies of RF high-efficiency power amplifiers. The book can be used as a guide by scientists and engineers dealing with the subject and as a text book for graduate and postgraduate students. Although primarily intended for skilled readers, it provides an excellent quick start for beginners.

How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The gm/ID methodology offers a solution provided a reference transconductance over drain current ratio is available. The reference may be the result of measurements carried out on real physical transistors or advanced models. The reference may also take advantage of a compact model. In The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.

Dynamic Offset-Compensated CMOS Amplifiers describes the theory, design and realization of dynamic offset compensated CMOS amplifiers. It focuses on the design of general-purpose wide-band operational amplifiers and instrumentation amplifiers.Two offset compensation techniques are described: auto-zeroing and chopping. Several topologies are discussed, with which these techniques can be used in the design of wide-band dynamic offset-compensated amplifiers. Four implementations are discussed in detail: two low-offset wide-band operational amplifiers, a low-offset instrumentation amplifier, and a low-offset current-sense amplifier, which can sense the current drawn from supply voltages up to 28V .

The RF power amplifier is a key component in a wireless transceiver and is considered by many as the design bottleneck in the transmitting chain. Linear CMOS RF Power Amplifiers for Wireless Applications addresses two fundamental aspects in RF power amplifier design for integration in CMOS technologies at 2.4, 3.7 and 5.2 GHz: efficiency enhancement and frequency agility.The well-known linearity-efficiency trade-off is circumvented by employing an efficiency-enhancement technique called the dynamic supply RF power amplifier. The design of this system is described with great detail and compared with other efficiency enhancement techniques.The frequency agility is achieved with a novel impedance matching network based on coupled inductors. The design of a dual-band RF power amplifier is shown, with a careful analysis of the tunable matching network and its interaction with the rest of the circuit.The considerations and conclusions drawn throughout this book are based on simulation as well as measurement results from the integrated circuit prototypes carefully built and respecting best practices in RF design.

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods.In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurementsfrom the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.

Biological visual systems employ massively parallel processing to perform real-world visual tasks in real time. A key to this remarkable performance seems to be that biological systems construct representations of their visual image data at multiple scales. A Pyramid Framework for Early Vision describes a multiscale, or `pyramid', approach to vision, including its theoretical foundations, a set of pyramid-based modules for image processing, object detection, texture discrimination, contour detection and processing, feature detection and description, and motion detection and tracking. It also shows how these modules can be implemented very efficiently on hypercube-connected processor networks. A Pyramid Framework for Early Vision is intended for both students of vision and vision system designers; it provides a general approach to vision systems design as well as a set of robust, efficient vision modules.